`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/06/16 15:02:16
// Design Name: 
// Module Name: adder
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module adder32x3(
    input [31:0] a,
    input [31:0] b,
    input [31:0] c,
    output [31:0] s,
    output [1:0] c2
);
    wire [33:0] s0;
    assign s0=a+b+c;
    assign s=s0[31:0];
    assign c2=s0[33:32];
endmodule

module adder32x2(
    input [31:0] a,
    input [31:0] b,
    output [31:0] s,
    output c1
    );
    assign {c1,s}=a+b;
endmodule

module adderx2w #(parameter WIDTH=32)(
    input [WIDTH-1:0] a,
    input [WIDTH-1:0] b,
    output [WIDTH-1:0] s,
    output c1
    );
    assign {c1,s}=a+b;
endmodule

module adder_carry_32x2(
    input [31:0] a,
    input [31:0] b,
    input cin,
    output [31:0] s
    );
    assign s=a+b+cin;
endmodule


